TEC0097 PCIe FMC carrier board hardware




Zynq PCIe FMC Carrier Evaluation Board for the Zynq-7000 XC7Z015 All Programmable SoC



User Manual
Version 1.0
03/09/2020
Document Number: 1.0
Revision History
The following table shows the revision history for this document

Date

Version



03/09/2020

1.0

Initial release


04/14/2020

1.1

updated figure 1

07/16/2021

1.2

AP SOC part number updated to XC7Z015-1CLG485C



TEC0097 Evaluation Board Features



Overview

The TEC0097 evaluation board for the XC7Z015 All Programmable SoC (AP SoC) provides a hardware environment for developing and evaluating designs targeting the Zynq™-7000 XC7Z015 -1CLG485C All Programmable SoC. The TEC0097 evaluation board provides features common to many embedded processing systems, including DDR3 component memory, one-lane PCI Express™ interface, GigaBit Ethernet PHY, general purpose I/O, and one USB-UART interfaces. Other features can be supported using VITA-57 FPGA mezzanine card (FMC) attached to the low pin count (LPC) FMC connectors.

TEC0097Evaluation Board Features

The TEC0097evaluation board features are listed in here. Detailed information for each feature is provided in next section.

  • Zynq-7000 XC7Z015-1CLG485C AP SoC

  • 1 GB DDR3 component memory (two [512 Mb x 16] devices) on the processing system (PS) side

  • A 256 Mb Quad-SPI flash memory

  • USB 2.0 ULPI (UTMI+ low pin interface) transceiver with micro-B USB connector

  • Secure Digital (SD) connector

  • Clock sources:

  • Fixed 125 MHz LVDS oscillator (differential)

  • Fixed 33.33 MHz LVCMOS oscillator connected to PS (single-ended)

  • Fixed 100.00 MHz LVCMOS oscillator connected to PL (single-ended)

  • GTP transceivers:

  • FMC LPC connector (one GTX transceiver)

  • PCI Express (1x lanes)

  • Small form-factor pluggable (SFP) connector

  • SATA Connector

  • PCI Express endpoint connectivity, Gen1 1-lane (x1)

  • SFP Connector

  • Ethernet PHY RGMII interface with RJ-45 connector

  • USB-to-UART bridge with mini-B USB connector

  • VGA codec with VGA connector

  • I2C bus

  • M24C08 EEPROM (1 kB)

  • FMC LPC connector

  • Quad SPI flash memory

  • USB JTAG configuration port (Digilent module)

  • Platform cable header JTAG configuration port

  • 20-pin TRENZ JTAG header

  • Dual 12-bit 1 MSPS XADC analog-to-digital front end

  • Status LEDs:

    • Ethernet status

    • Power

    • 12V Input Power On

    • FPGA INIT

    • FPGA DONE

  • User I/O:

    • Four (PL) user LEDs

    • One (PL) user pushbuttons

    • One (PL) user DIP switch (4-pole)

    • Two Dual row Pmod GPIO headers

    • AP SoC PS Reset Pushbuttons:

    • SRST_B PS reset button

    • POR_B PS reset button

    • VITA 57.1 FMC LPC connector

    • Power on/off slide switch

 

Block Diagram

The TEC0097 evaluation board block diagram is shown in Figure ‎1 1.

 



 


{*}Figure ‎1* 1: TEC0097 Evaluation Board Block Diagram

Board Layout

Figure ‎1 2 shows the TEC0097 evaluation board. Each numbered feature that is referenced in Figure ‎1 2 is described in Table 1-1 with associated schematic pages. For more detail please refer to provided schematic data.
Note: The image in Figure ‎1 2 is for reference only and might not reflect the current revision of the board.
CAUTION! The TEC0097 evaluation board can be damaged by electrostatic discharge (ESD). Follow ESD prevention measures when handling the board.


{*}Figure ‎1* 2: TEC0097Evaluation Board Component Locations

{*}Table ‎1* 1: TEC0097 Evaluation Board Component Descriptions

Callout

Feature

Note

Schematic Page Number

1

ZYNQ XC7Z015-1CLG485C



5, 6, 7, 8, 9, 10, 11

2

VITA 57.1 FMC LPC



16

3

PCIe x1



17

4

DDR3 & DDR Termination



4, 18

5

SFP



15

6

PS, PL-side GPIO



26

7

Power



3, 25

8

USB UART



12

9

USB OTG



19

10

SD Card



14

11

Gigabit Ethernet



20

12

VGA out



21

13

Boot mode, QSPI memory



6

Feature Descriptions

The TEC0097 evaluation board is populated with the Zynq-7000 XC7Z015-1CLG485C AP SoC. The XC7Z015 AP SoC consists of an integrated processing system (PS) and programmable logic (PL), on a single die. The high-level block diagram is shown in Figure ‎1 3

{*}Figure ‎1* 3: High-Level Block Diagram
The PS integrates two ARM® Cortex™-A9 MPCore™ application processors, AMBA® interconnect, internal memories, external memory interfaces, and peripherals including USB, Ethernet, SPI, SD/SDIO, I2C, CAN, UART, and GPIO. The PS runs independently of the PL and boots at power-up or reset. A system level block diagram is shown in Figure ‎1 4.

{*}Figure ‎1* 4: Zynq-7000 Block Diagram
For additional information on Zynq-7000 SoC devices, see Zynq-7000 All Programmable SoC Overview (DS190) and Zynq-7000 All Programmable SoC Technical Reference Manual (UG585).
Following is quick description for technical feature of the TEC0097 evaluation board, for more detail refer to schematic pages.

Device Configuration and Booting

The Zynq-7000 XC7Z015 AP SoC uses a multi-stage boot process that supports both a non-secure and a secure boot. The PS is the master of the boot and configuration process. For a secure boot, the PL must be powered on to enable the use of the security block located within the PL, which provides 256-bit AES and SHA decryption/authentication. Figure ‎1 5 shows three different source for configuration and boot data.

{*}Figure ‎1* 5: The XC7Z015 Configuration data source
The TEC0097 evaluation board supports these configuration options:

  • PS Configuration: Quad-SPI flash memory

  • PS Configuration: Processor System Boot from SD Card (J10)

  • PL Configuration: USB JTAG configuration port (U11)

  • PL Configuration: Platform cable header P2 JTAG configuration ports

The configuration option is selected by setting S7 (PS) as shown in Table ‎1 2.
{*}Table ‎1* 2: Switch S7 Configuration Option Settings

Boot Mode

SW7.1

SW7.2

Comment

JTAG

0

0

1: ON, 0: OFF

QSPI

1

0

1: ON, 0: OFF

SD

1

1

1: ON, 0: OFF


For more information about Zynq-7000 AP SoC configuration settings, see Zynq-7000 All Programmable SoC Technical Reference Manual (UG585).

I/O Voltage Rails

There are seven section and I/O banks available on the XC7Z015 AP SoC. The voltages applied to the XC7Z015 AP SoC sections and I/O banks used by the TEC0097 evaluation board are listed in Table ‎1 3.
{*}Table ‎1* 3: The voltages applied to the XC7Z015 AP SoC sections and I/O banks

Bank Name

PL/PS/MGT

Application

Voltage

Comment

MIO 500

PS

QSPI/PS-GPIO

Fixed 3.3V



MIO 501

PS

Ethernet/USB-OTG/SD/UART/I2C

Fixed 1.8V



MIO 502

PS

PS DDR memory interface

Fixed 1.5V



Bank 13

PL

VGA/RS485/GPIO/SFP

Fixed 3.3V



Bank 34

PL

FMC/PL-GPIO

Adgustable 1.2-3.3V



Bank 35

PL

FMC/PMOD

Adgustable 1.2-3.3V



MGT_112

MGT

PCIe/SFP/SATA/FMC-GTX

Fixed 1.2V



DDR3 Component Memory (PS)

The 1 GB, 32-bit wide DDR3 component memory system is comprised of two 512 Mb x 16 SDRAMs (Micron MT41K256M16HA-125) at U9-U10. This memory system is connected to the XC7Z015 AP SoC Processing System (PS) memory interface bank 502. The DDR3 0.75V VTT termination voltage is sourced from linear regulator U13.

{*}Figure ‎1* 6: DDR3 memory to XC7Z015 connection and termination
The connections between the DDR3 component memory and XC7Z015 AP SoC bank 502 are listed in Table ‎1 4.
{*}Table ‎1* 4: The connections between the DDR3 component memory and XC7Z015 AP SoC bank 502

Pin Designator

Pin Name

Net

Type

Bank No.

Bank Voltage

Comment

M19

PS_DDR_A0_502

DDR3_A0

Output

MIO 502

1.5V



M18

PS_DDR_A1_502

DDR3_A1

Output

MIO 502

1.5V



J20

PS_DDR_A10_502

DDR3_A10

Output

MIO 502

1.5V



G18

PS_DDR_A11_502

DDR3_A11

Output

MIO 502

1.5V



H19

PS_DDR_A12_502

DDR3_A12

Output

MIO 502

1.5V



F19

PS_DDR_A13_502

DDR3_A13

Output

MIO 502

1.5V



G19

PS_DDR_A14_502

DDR3_A14

Output

MIO 502

1.5V



K19

PS_DDR_A2_502

DDR3_A2

Output

MIO 502

1.5V



L19

PS_DDR_A3_502

DDR3_A3

Output

MIO 502

1.5V



K17

PS_DDR_A4_502

DDR3_A4

Output

MIO 502

1.5V



K18

PS_DDR_A5_502

DDR3_A5

Output

MIO 502

1.5V



J16

PS_DDR_A6_502

DDR3_A6

Output

MIO 502

1.5V



J17

PS_DDR_A7_502

DDR3_A7

Output

MIO 502

1.5V



J18

PS_DDR_A8_502

DDR3_A8

Output

MIO 502

1.5V



H18

PS_DDR_A9_502

DDR3_A9

Output

MIO 502

1.5V



L16

PS_DDR_BA0_502

DDR3_BA0

Output

MIO 502

1.5V



L17

PS_DDR_BA1_502

DDR3_BA1

Output

MIO 502

1.5V



M17

PS_DDR_BA2_502

DDR3_BA2

Output

MIO 502

1.5V



P20

PS_DDR_CAS_B_502

DDR3_CAS#

Output

MIO 502

1.5V



N18

PS_DDR_CKN_502

DDR3_CK_N

Output

MIO 502

1.5V



N19

PS_DDR_CKP_502

DDR3_CK_P

Output

MIO 502

1.5V



T19

PS_DDR_CKE_502

DDR3_CKE

Output

MIO 502

1.5V



P17

PS_DDR_CS_B_502

DDR3_CS#

Output

MIO 502

1.5V



D22

PS_DDR_DQ0_502

DDR3_D0

I/O

MIO 502

1.5V



C20

PS_DDR_DQ1_502

DDR3_D1

I/O

MIO 502

1.5V



L22

PS_DDR_DQ10_502

DDR3_D10

I/O

MIO 502

1.5V



L21

PS_DDR_DQ11_502

DDR3_D11

I/O

MIO 502

1.5V



L20

PS_DDR_DQ12_502

DDR3_D12

I/O

MIO 502

1.5V



K22

PS_DDR_DQ13_502

DDR3_D13

I/O

MIO 502

1.5V



J22

PS_DDR_DQ14_502

DDR3_D14

I/O

MIO 502

1.5V



K20

PS_DDR_DQ15_502

DDR3_D15

I/O

MIO 502

1.5V



M22

PS_DDR_DQ16_502

DDR3_D16

I/O

MIO 502

1.5V



T20

PS_DDR_DQ17_502

DDR3_D17

I/O

MIO 502

1.5V



N20

PS_DDR_DQ18_502

DDR3_D18

I/O

MIO 502

1.5V



T22

PS_DDR_DQ19_502

DDR3_D19

I/O

MIO 502

1.5V



B21

PS_DDR_DQ2_502

DDR3_D2

I/O

MIO 502

1.5V



R20

PS_DDR_DQ20_502

DDR3_D20

I/O

MIO 502

1.5V



T21

PS_DDR_DQ21_502

DDR3_D21

I/O

MIO 502

1.5V



M21

PS_DDR_DQ22_502

DDR3_D22

I/O

MIO 502

1.5V



R22

PS_DDR_DQ23_502

DDR3_D23

I/O

MIO 502

1.5V



Y20

PS_DDR_DQ24_502

DDR3_D24

I/O

MIO 502

1.5V



U22

PS_DDR_DQ25_502

DDR3_D25

I/O

MIO 502

1.5V



AA22

PS_DDR_DQ26_502

DDR3_D26

I/O

MIO 502

1.5V



U21

PS_DDR_DQ27_502

DDR3_D27

I/O

MIO 502

1.5V



W22

PS_DDR_DQ28_502

DDR3_D28

I/O

MIO 502

1.5V



W20

PS_DDR_DQ29_502

DDR3_D29

I/O

MIO 502

1.5V



D20

PS_DDR_DQ3_502

DDR3_D3

I/O

MIO 502

1.5V



V20

PS_DDR_DQ30_502

DDR3_D30

I/O

MIO 502

1.5V



Y22

PS_DDR_DQ31_502

DDR3_D31

I/O

MIO 502

1.5V



E20

PS_DDR_DQ4_502

DDR3_D4

I/O

MIO 502

1.5V



E22

PS_DDR_DQ5_502

DDR3_D5

I/O

MIO 502

1.5V



F21

PS_DDR_DQ6_502

DDR3_D6

I/O

MIO 502

1.5V



F22

PS_DDR_DQ7_502

DDR3_D7

I/O

MIO 502

1.5V



G21

PS_DDR_DQ8_502

DDR3_D8

I/O

MIO 502

1.5V



G22

PS_DDR_DQ9_502

DDR3_D9

I/O

MIO 502

1.5V



B22

PS_DDR_DM0_502

DDR3_DM0

Output

MIO 502

1.5V



H20

PS_DDR_DM1_502

DDR3_DM1

Output

MIO 502

1.5V



P22

PS_DDR_DM2_502

DDR3_DM2

Output

MIO 502

1.5V



AA21

PS_DDR_DM3_502

DDR3_DM3

Output

MIO 502

1.5V



D21

PS_DDR_DQS_N0_502

DDR3_DQ0_N

I/O

MIO 502

1.5V



C21

PS_DDR_DQS_P0_502

DDR3_DQ0_P

I/O

MIO 502

1.5V



J21

PS_DDR_DQS_N1_502

DDR3_DQ1_N

I/O

MIO 502

1.5V



H21

PS_DDR_DQS_P1_502

DDR3_DQ1_P

I/O

MIO 502

1.5V



P21

PS_DDR_DQS_N2_502

DDR3_DQ2_N

I/O

MIO 502

1.5V



N21

PS_DDR_DQS_P2_502

DDR3_DQ2_P

I/O

MIO 502

1.5V



W21

PS_DDR_DQS_N3_502

DDR3_DQ3_N

I/O

MIO 502

1.5V



V21

PS_DDR_DQS_P3_502

DDR3_DQ3_P

I/O

MIO 502

1.5V



P18

PS_DDR_ODT_502

DDR3_ODT

Output

MIO 502

1.5V



R18

PS_DDR_RAS_B_502

DDR3_RAS#

Output

MIO 502

1.5V



F20

PS_DDR_DRST_B_502

DDR3_RESET#

Output

MIO 502

1.5V



H16

PS_DDR_VREF0_502

DDR3_VREF

Input

MIO 502

1.5V



P16

PS_DDR_VREF1_502

DDR3_VREF

Input

MIO 502

1.5V



R19

PS_DDR_WE_B_502

DDR3_WE#

Output

MIO 502

1.5V



M16

PS_DDR_VRN_502

NetR124_1

Output

MIO 502

1.5V



N16

PS_DDR_VRP_502

NetR125_1

Output

MIO 502

1.5V




The TEC0097 DDR3 component interface adheres to the constraints guidelines documented in the DDR3 Design Guidelines section of Zynq-7000 All Programmable SoC PCB Design and Pin Planning Guide (UG933). The TEC0097 DDR3 component interface is a 40Ω impedance implementation. For more details, see the MT41K256M16HA-125 data sheet.
Note: The actual on-board DDR3 memory device component may differ based on revision of the board, and alternative components.

Quad-SPI Flash Memory

The Quad-SPI flash memory located at U8 provides 256 Mb of nonvolatile storage that can be used for configuration and data storage.

  • Part number: N25Q256A11ESF40G (Micron)

  • Supply voltage: 3.3V

  • Datapath width: 4 bits

  • Data rate: Various depending on Single/Dual/Quad mode

The flash memory is mapped to Quad SPI 0 IP controller block within the XC7Z015 AP SoC PS I/O Peripherals set, and connection detail between the Quad-SPI flash memory and the XC7Z015 AP SoC and bank no. and voltage are listed in Table ‎1 5.
{*}Table ‎1* 5: The connections between the SPI flash memory and the XC7Z015 AP SoC

Pin Designator

Pin Name

Net

Type

Bank No.

Bank Voltage

Comment

A22

PS_MIO1_500

SPI_CS

I/O

MIO-500

3.3V



A21

PS_MIO2_500

SPI_DQ0/MIO2

I/O

MIO-500

3.3V



F17

PS_MIO3_500

SPI_DQ1/MIO3

I/O

MIO-500

3.3V



E19

PS_MIO4_500

SPI_DQ2/MIO4

I/O

MIO-500

3.3V



A20

PS_MIO5_500

SPI_DQ3/MIO5

I/O

MIO-500

3.3V



A19

PS_MIO6_500

SPI_SCK/MIO6

I/O

MIO-500

3.3V





USB 2.0 Connection

The TEC0097 evaluation board uses two independent USB connections, USB 2.0 ULPI OTG and USB UART bridge. Figure ‎1 7 shows the simple connection concept.

{*}Figure ‎1* 7: USB to TEC0097 connections

USB 2.0 ULPI Transceiver

The TEC0097 evaluation board uses a Standard Microsystems Corporation USB3320 USB 2.0 ULPI Transceiver at U22 to support a USB connection to the host computer. A USB cable is supplied in the TEC0097 evaluation kit (Standard-A connector to host computer, Micro-B connector to TEC0097 evaluation board connector J6). The USB3320 is a high-speed USB 2.0 PHY supporting the UTMI+ low pin interface (ULPI) interface standard. The ULPI standard defines the interface between the USB controller IP and the PHY device which drives the physical USB bus. Use of the ULPI standard reduces the interface pin count between the USB controller IP and the PHY device.
The USB3320 is clocked by a 24 MHz crystal. Consult the SMSC USB3320 data sheet for clocking mode details. The interface to the USB3320 transceiver is implemented through the IP in the XC7Z015 AP SoC Processor System. Note that the shield for the USB Micro-B connector (J6) tied to GND.
The USB3320 is connected to USB 0 IP controller block within the XC7Z015 AP SoC PS I/O Peripherals set, and connections between the USB3320 USB 2.0 ULPI Transceiver and the XC7Z015 AP SoC and bank no. and voltage are listed in Table ‎1 6.
{*}Table ‎1* 6: The connections between the USB3320 USB 2.0 ULPI Transceiver and the XC7Z015 AP SoC

Pin Designator

Pin Name

Net

Type

Part No.

Bank Voltage

Comment

A14

PS_MIO36_501

OTG_CLK

I/O

MIO 501

1.8V



C16

PS_MIO32_501

OTG_DATA0

I/O

MIO 501

1.8V



G11

PS_MIO33_501

OTG_DATA1

I/O

MIO 501

1.8V



B11

PS_MIO34_501

OTG_DATA2

I/O

MIO 501

1.8V



F9

PS_MIO35_501

OTG_DATA3

I/O

MIO 501

1.8V



A11

PS_MIO28_501

OTG_DATA4

I/O

MIO 501

1.8V



B9

PS_MIO37_501

OTG_DATA5

I/O

MIO 501

1.8V



F10

PS_MIO38_501

OTG_DATA6

I/O

MIO 501

1.8V



C10

PS_MIO39_501

OTG_DATA7

I/O

MIO 501

1.8V



E15

PS_MIO29_501

OTG_DIR

I/O

MIO 501

1.8V



F14

PS_MIO31_501

OTG_NXT

I/O

MIO 501

1.8V



A12

PS_MIO30_501

OTG_STP

I/O

MIO 501

1.8V





USB-to-UART Bridge

The TEC0097 evaluation board contains a FTDI FT2232H dual channel USB-to-UART/FIFO/JTAG bridge device (U11) which allows two connections to a host computer with a single USB port. The USB cable is supplied in the ZPFC evaluation kit (Standard-A end to host computer, Type Mini-B end to ZPFC evaluation board connector J11).
The channel B of FT2232H TX and RX pins are wired to the UART_0 IP block within the XC7Z015 AP SoC PS I/O Peripherals set. The XC7Z015 AP SoC supports the USB-to-UART bridge using two signal pins: Transmit (TX) and Receive (RX).
The FTDI provides royalty-free Virtual COM Port (VCP) drivers for the host computer. This driver permit the FT2232H USB-to-UART bridge to appear as a COM port to communications application software (for example, TeraTerm or HyperTerm) that runs on the host computer. The VCP device drivers must be installed on the host PC prior to establishing communications with the TEC0097 evaluation board.
Table ‎1 7 lists the USB connections between the XC7Z015 AP SoC PS Bank 501 and the FT2232H UART bridge.
{*}Table ‎1* 7: USB connections between the XC7Z015 AP SoC PS Bank 501 and the FT2232H

Pin Designator

Pin Name

Net

Type

Bank No.

Bank Voltage

Comment

D11

PS_MIO46_501

USB_UART_RX

I/O

MIO 501

1.8V



B13

PS_MIO47_501

USB_UART_TX

I/O

MIO 501

1.8V




Refer to the Future Technology Devices International Ltd website for technical information on the FT2232H and the VCP drivers. For additional information on the Zynq-7000 AP SoC device UART controller, see Zynq-7000 All Programmable SoC Overview (DS190) and Zynq-7000 All Programmable SoC Technical Reference Manual (UG585).

RS-485/RS-422 Interface

The TEC0097 evaluation board includes ADM3078E RS-485/RS-422 transceivers, which logic interface connected to PL-side. The RS-485/RS-422 interface is half-duplex with differential signals, terminated at 120 ohm, are available at J16.
The Analog Devices ADM3078E at U18 is 3.3 V, low power data transceivers with ±15 kV ESD protection suitable for half-duplex communication on multipoint bus transmission lines. It is designed for balanced data transmission, and they comply with TIA/EIA standards: RS-485 and RS-422. Figure ‎1 8 show circuit diagram detail for RS-485/RS-422 interface.

{*}Figure ‎1* 8: Circuit diagram for RS-485/RS-422 interface
Table ‎1 8 lists the RS-485/RS-422 interface connections to the XC7Z015 AP SoC.
{*}Table ‎1* 8: the RS-485/RS-422 interface connections to the XC7Z015

Pin Designator

Pin Name

Net

Type

Bank No.

Bank Voltage

Comment

AB22

IO_L15N_T2_DQS_13

RS485_CH1_REN

I/O

13

3.3V



AB21

IO_L15P_T2_DQS_13

RS485_CH1_RXD

I/O

13

3.3V



AA19

IO_L18P_T2_13

RS485_CH1_TXD

I/O

13

3.3V



For additional information on ADM3078E transceivers, see associated datasheet at Analog Devices.

SD Card Interface

The TEC0097 evaluation board includes a secure digital input/output (SDIO) interface to provide user-logic access to general purpose nonvolatile SDIO memory cards and peripherals. The SDIO signals are connected to XC7Z015 AP SoC PS bank 501 which has its VCCMIO set to 1.8V. A TI TXS02612RTWR high-speed logic-level translator (U19) is used between XC7Z015 AP SoC 1.8V PS bank 501 and the 3.3V micro SD card connector (J10).
Figure ‎1 8 shows the connections of the SD card interface on the TEC0097 evaluation board.

{*}Figure ‎1* 9: SD card interface on the TEC0097 evaluation board
The micro SD card is connected to SDIO 0 IP controller block within the XC7Z015 AP SoC PS I/O Peripherals set. Table ‎1 9 lists the micro SD card interface connections to the XC7Z015 AP SoC.
{*}Table ‎1* 9: The connections between the micro SD and the XC7Z015 AP SoC

Pin Designator

Pin Name

Net

Type

Bank No.

Bank Voltage

Comment

E9

PS_MIO40_501

SD_CLK_LS

I/O

MIO 501

1.8V



G17

PS_MIO0_500

SD_CD

I/O

MIO 500

3.3V



C15

PS_MIO41_501

SD_CMD_LS

I/O

MIO 501

1.8V



D15

PS_MIO42_501

SD_DATA0_LS

I/O

MIO 501

1.8V



B12

PS_MIO43_501

SD_DATA1_LS

I/O

MIO 501

1.8V



E10

PS_MIO44_501

SD_DATA2_LS

I/O

MIO 501

1.8V



B14

PS_MIO45_501

SD_DATA3_LS

I/O

MIO 501

1.8V



The SD_CD card detection signal is connected to PS_MIO0_501. The active low on this input is to indicate the card is inserted.

JTAG Programming Processor and Programmable Logic

The JTAG connectivity on the TEC0097 board allows a host computer to download bitstreams to the AP SoC using the Xilinx® iMPACT software. In addition, the JTAG connector allows debug tools such as the Vivado serial I/O analyzer or a software debugger to access the SoC. The iMPACT software tool can also indirectly program the linear QSPI flash memory. To accomplish this, the iMPACT software configures the SoC with a temporary design to access and program the QSPI memory device
The TEC0097 evaluation board uses JTAG for PS and PL programming, The JTAG chain is shown in Figure ‎1 9.

{*}Figure ‎1* 10: TEC0097 JTAG chain

Programmable Logic JTAG Select Switch

The PL JTAG chain can be programmed by three different methods: the 14-pin header J3 for configuration using either a Parallel Cable IV (PC4) or Platform Cable USB II, the USB-to-JTAG bridge U11 for configuration over a Standard-A to Micro-B USB cable (optional), and Trenz TE0790 USB-to-JTAG bridge for configuration (optional).

FMC Connector JTAG Bypass

When an FPGA mezzanine card (FMC) is attached to LPC J5 it may be added to the JTAG chain if FMC connector JTAG bypass is removed. The attached FMC card must implement a TDI-to-TDO connection through a device or bypass jumper for the JTAG chain to be completed to the AP SoC U6. If FMC not attached or JTAG is not implemented on FMC, the bypass jumper should be inserted to complete the chain.

Clock Source Generation

The TEC0097 evaluation board provides three clock sources for the XC7Z015 AP SoC. Figure ‎1 10 lists the connections from each clock source to the XC7Z015 AP SoC and lists the source devices for each clock.

{*}Figure ‎1* 11: Clock distribution in TEC0097

Processing System Clock Source

The Processing System (PS) clock source is a 3.3V LVCMOS single-ended fixed 33.33333 MHz oscillator at U7. It is wired to PS bank 500, pin F16 (PS_CLK), on the XC7Z015 AP SoC. Refer to Table ‎1 10 for detail of clock source connection to XC7Z015.

System Clock

The system clock source is a 3.3V LVCMOS single-ended fixed 100.00 MHz oscillator at U14. It is wired to a multi-region clock capable (MRCC) input on programmable logic (PL) bank 13. The signal is named PL_CLK and signal is connected to U6 pin Y14 on the XC7Z015 AP SoC. Table ‎1 10 shows detail of clock source connection to XC7Z015.
{*}Table ‎1* 10: Clock source connection to XC7Z015

Pin Designator

Pin Name

Net

Type

Bank No.

Bank Voltage

Comment

Y14

IO_L12P_T1_MRCC_13

PL_CLK

I/O

13

3.3V



F16

PS_CLK_500

CLK_PS_33MHZ

Input

MIO 500

3.3V



GTP Transceivers

The 7z015 devices includes 4 GTP low-power serial transceivers that can operate up to 6.25 Mb/s per transceiver. Figure 21-14 shows the placement diagram for the XC7Z015-CLG485 dual core devices.

{*}Figure ‎1* 12: GTP placement diagram for the XC7Z015-CLG485
The TEC0097 evaluation board provides access to 4 GTP transceivers:

  • One of the GTP transceivers are wired to the PCI Express x1 endpoint edge connector fingers (J4)

  • One GTP transceiver is wired to the FMC LPC connector (J2)

  • One GTP transceiver is wired to the SFP Module connector (J1)

  • One GTP transceiver is wired to the SATA connector (J15)

The GTP transceivers in Zynq-7000 series AP SoCs are grouped into four channels described as Quads. The reference clock for the Quad can be sourced from PCI Express edge connector or on board 125MHZ LVDS clock source. There is one GTP Quad on the XC7Z015-CLG485 with connectivity as shown here:
• Quad 112:

  • MGTREFCLK0 – PCIe input clock PECLKIN_P/N

  • MGTREFCLK1 – on-board 125Mhz LVDS clock input, CLK_Diff_P/N

  • Channel 0 GTP transceiver allocated to PCIe PER0_P/N and PET0_P/N

  • Channel 1 GTP transceiver allocated to FMC DP0_M2C_P/N and DP0_C2M_P/N

  • Channel 2 GTP transceiver allocated to SATA RX/TX_P/N

  • Channel 3 GTP transceiver allocated to SFPTX and RX_P/N SFP connector

Table ‎1 11 lists the GTP Banks 112 interface connections between the AP SoC U1 and PCIe, FMC LPC, SATA, and SFP connector.
{*}Table ‎1* 11: GTP connections between the AP SoC and PCIe, FMC LPC, SATA, and SFP connector

Pin Designator

Pin Name

Net

Type

Bank No.

Bank Voltage

Comment

V5

MGTREFCLK1N_112

CLK_DIFF_N

Input

112





U5

MGTREFCLK1P_112

CLK_DIFF_P

Input

112





V9

MGTREFCLK0N_112

PECLKIN_N

Input

112





U9

MGTREFCLK0P_112

PECLKIN_P

Input

112





Y4

MGTXTXN1_112

DP0_C2M_N

Output

112





W4

MGTXTXP1_112

DP0_C2M_P

Output

112





Y8

MGTXRXN1_112

DP0_M2C_N

Input

112





W8

MGTXRXP1_112

DP0_M2C_P

Input

112





AB7

MGTXRXN0_112

PER0_N

Input

112





AA7

MGTXRXP0_112

PER0_P

Input

112





AB3

MGTXTXN0_112

PET0_N

Output

112





AA3

MGTXTXP0_112

PET0_P

Output

112





AB9

MGTXRXN2_112

SATA0_RX_N

Input

112





AA9

MGTXRXP2_112

SATA0_RX_P

Input

112





AB5

MGTXTXN2_112

SATA0_TX_N

Output

112





AA5

MGTXTXP2_112

SATA0_TX_P

Output

112





Y6

MGTXRXN3_112

SFPRX_N

Input

112





W6

MGTXRXP3_112

SFPRX_P

Input

112





Y2

MGTXTXN3_112

SFPTX_N

Output

112





W2

MGTXTXP3_112

SFPTX_P

Output

112





AA14

IO_L11P_T1_SRCC_13

PERST_N

I/O

13

3.3V





PCI Express Endpoint Connectivity

The TEC0097evaluation board provides 1-lane PCI Express™ edge connector which can performs data transfers at the rate of 2.5 GT/s for a Gen1 application and 5.0 GT/s for a Gen2 application. The PCI Express transmit and receive signal data paths have a characteristic impedance of 100Ω ±10%. The PCI Express clock is routed as a 100Ω differential pair. The TEC0097 board which assembled with XC7Z015-1CLG485C AP SoC (-1 speed grade) supports up to Gen1, while XC7Z015-2FFG485C AP SoC (-2 speed grade) supports up to Gen2. The PCI Express clock is input from the edge connector. It is AC coupled to the AP SoC through the MGTREFCLK0 pins of Quad 112 of AP SoC U6.
For additional information about Zynq-7000 PCIe functionality, see 7 Series FPGAs Integrated Block for PCI Express Product Guide for Vivado Design Suite (PG054). Additional information about the PCI Express standard.

SFP Module Connector

The TEC0097 board contains a small form-factor pluggable (SFP) connector and cage assembly at J1 that accepts SFP modules. The SFP require a GTP transceivers and some LVTTL controlling or status lines. Figure ‎1 12 shows the SFP module connector circuitry.

{*}Figure ‎1* 13: SFP module connector circuitry
The SFP's RX TX signals are connected to Quad 112, and LVTTL controlling or status lines are connected to PL side of AP SoC U6. Table ‎1 11 lists the SFP module RX and TX connections, and Table ‎1 12 list the LVTTL connection to the AP SoC.
{*}Table ‎1* 12: SFP module LVTTL connection to the AP SoC

Pin Designator

Pin Name

Net

Type

Bank No.

Bank Voltage

Comment

W12

IO_L3P_T0_DQS_13

SFP_LED_RX

I/O

13

3.3V



U12

IO_L5N_T0_13

SFP_LED_TX

I/O

13

3.3V



Y12

IO_L10P_T1_13

SFP_LOS

I/O

13

3.3V



AA12

IO_L8P_T1_13

SFP_MOD_DEF0

I/O

13

3.3V



U11

IO_L5P_T0_13

SFP_MOD_DEF1

I/O

13

3.3V



W11

IO_L4N_T0_13

SFP_MOD_DEF2

I/O

13

3.3V



V11

IO_L4P_T0_13

SFP_RATE_SELECT

I/O

13

3.3V



AB11

IO_L7N_T1_13

SFP_TX_DISABLE

I/O

13

3.3V



AA11

IO_L7P_T1_13

SFP_TX_FAULT

I/O

13

3.3V



Note: The SFP module is not included, and must be ordered separately.

SATA Connector

The TEC0097 evaluation board accommodate a SATA connector at J15. The XC7Z015-1FFG485C AP SoC does not support Serial ATA directly. User may implement own SATA controller in the PL side. Figure ‎1 13 shows SATA connector signals, connection detail to the XC7Z015 is included in Table ‎1 11.

{*}Figure ‎1* 14: SATA connector signals

10/100/1000 Mb/s Tri-Speed Ethernet PHY (PS)

The XC7Z015 support two Gigabit Ethernet Media Access Controller (MAC) on PS. The TEC0097 evaluation board uses the TI PHY device (DP83867CRRGZT) at U15 for Ethernet communications with MAC at 10 Mb/s, 100 Mb/s, or 1000 Mb/s, which is connected to Ethernet 0 IP controller block within the XC7Z015 AP SoC PS I/O Peripherals set. The on-board connection supports RGMII mode only. The PHY connection to a user-provided Ethernet cable is through a Halo L829-1J1T-43 RJ-45 connector (P1) with built-in magnetics. On power-up, or on reset, the PHY is configured to operate in RGMII mode with PHY address 0b00111 using the resistor strap settings. These settings can be overwritten via software commands passed over the MDIO interface. A 25.00 MHz 50 ppm crystal at Y2 is the clock source for the DP83867CRRGZT PHY at U15. Figure ‎1 14 shows Gigabit Ethernet PHY to XC7Z015 connection.

{*}Figure ‎1* 15: Gigabit Ethernet PHY to XC7Z015 connection
The Ethernet connections from the XC7Z015 AP SoC MIO 501 at U6 to the DP83867CRRGZT PHY device at U15 are listed in Table ‎1 13.
{*}Table ‎1* 13: The connections from the XC7Z015 AP SoC to the DP83867CRRGZT PHY device

Pin Designator

Pin Name

Net

Type

Bank No.

Bank Voltage

Comment

D13

PS_MIO52_501

MDC

I/O

MIO 501

1.8V



C11

PS_MIO53_501

MDIO

I/O

MIO 501

1.8V



A9

PS_MIO22_501

RX_CLK

I/O

MIO 501

1.8V



D16

PS_MIO27_501

RX_CTRL

I/O

MIO 501

1.8V



E12

PS_MIO23_501

RX_D0

I/O

MIO 501

1.8V



B16

PS_MIO24_501

RX_D1

I/O

MIO 501

1.8V



F11

PS_MIO25_501

RX_D2

I/O

MIO 501

1.8V



A10

PS_MIO26_501

RX_D3

I/O

MIO 501

1.8V



D17

PS_MIO16_501

GTX_CLK

I/O

MIO 501

1.8V



F12

PS_MIO21_501

TX_CTRL

I/O

MIO 501

1.8V



E14

PS_MIO17_501

TX_D0

I/O

MIO 501

1.8V



A16

PS_MIO18_501

TX_D1

I/O

MIO 501

1.8V



E13

PS_MIO19_501

TX_D2

I/O

MIO 501

1.8V



A15

PS_MIO20_501

TX_D3

I/O

MIO 501

1.8V



The three Ethernet PHY user LEDs shown in Figure ‎1 14 are located in front face and top right and left side the RJ45 Ethernet jack L829-1J1T-43 at P1. The on/off state for each LED is software dependent and has specific meaning at Ethernet PHY power on, Figure ‎1 15 shows assigned functions.

{*}Figure ‎1* 16: Ethernet LEDs
For more detail refer to TI's DP83867CRRGZT datasheet.

VGA Video Output

The TEC0097 evaluation board provides a Video Graphics Array (VGA) video output using an Analog Devices ADV7125KSTZ140 VGA video DAC at U16. The VGA video DAC U16 is connected to the XC7Z015 AP SoC PL-side bank 13 and its analog output is provided on a DSUB15 VGA receptacle at J14. The ADV7125KSTZ140 supports RGB encoding via 24-bit input data mapping. Along color data, horizontal and vertical sync data is also available on connector. Figure ‎1 15 shows data flow in the simple form.

{*}Figure ‎1* 17: Connection and data flow for VGA
The TEC0097 evaluation board supports the following VGA device interfaces:

  • 24 data lines

  • Independent VSYNC, HSYNC

  • Single-ended input CLK

The connections between the ADV7125KSTZ140 VGA video DAC and the XC7Z015 AP SoC PL-side bank 13 and voltage are listed in Table ‎1 6.
{*}Table ‎1* 14: The connections between the ADV7125KSTZ140 VGA video DAC and the XC7Z015 AP SoC PL-side bank 13

Pin Designator

Pin Name

Net

Type

Bank No.

Bank Voltage

Comment

T17

IO_L19N_T3_VREF_13

VIDEO_OUT1_B0

I/O

13

3.3V



U19

IO_L20P_T3_13

VIDEO_OUT1_B1

I/O

13

3.3V



V18

IO_L21P_T3_DQS_13

VIDEO_OUT1_B2

I/O

13

3.3V



R17

IO_L19P_T3_13

VIDEO_OUT1_B3

I/O

13

3.3V



T16

IO_0_13

VIDEO_OUT1_B4

I/O

13

3.3V



V15

IO_L2P_T0_13

VIDEO_OUT1_B5

I/O

13

3.3V



V14

IO_L1N_T0_13

VIDEO_OUT1_B6

I/O

13

3.3V



W13

IO_L3N_T0_DQS_13

VIDEO_OUT1_B7

I/O

13

3.3V



Y19

IO_L13N_T2_MRCC_13

VIDEO_OUT1_BLANK

I/O

13

3.3V



V13

IO_L1P_T0_13

VIDEO_OUT1_CLK

I/O

13

3.3V



V19

IO_L20N_T3_13

VIDEO_OUT1_G0

I/O

13

3.3V



Y13

IO_L10N_T1_13

VIDEO_OUT1_G1

I/O

13

3.3V



AA15

IO_L11N_T1_SRCC_13

VIDEO_OUT1_G2

I/O

13

3.3V



V16

IO_L23P_T3_13

VIDEO_OUT1_G3

I/O

13

3.3V



W16

IO_L23N_T3_13

VIDEO_OUT1_G4

I/O

13

3.3V



W17

IO_L24P_T3_13

VIDEO_OUT1_G5

I/O

13

3.3V



W18

IO_L21N_T3_DQS_13

VIDEO_OUT1_G6

I/O

13

3.3V



U17

IO_L22P_T3_13

VIDEO_OUT1_G7

I/O

13

3.3V



AB16

IO_L17P_T2_13

VIDEO_OUT1_HSYNC

I/O

13

3.3V



AA16

IO_L14P_T2_SRCC_13

VIDEO_OUT1_R0

I/O

13

3.3V



U14

IO_L6N_T0_VREF_13

VIDEO_OUT1_R1

I/O

13

3.3V



U13

IO_L6P_T0_13

VIDEO_OUT1_R2

I/O

13

3.3V



W15

IO_L2N_T0_13

VIDEO_OUT1_R3

I/O

13

3.3V



U16

IO_25_13

VIDEO_OUT1_R4

I/O

13

3.3V



Y17

IO_L24N_T3_13

VIDEO_OUT1_R5

I/O

13

3.3V



U18

IO_L22N_T3_13

VIDEO_OUT1_R6

I/O

13

3.3V



AA20

IO_L18N_T2_13

VIDEO_OUT1_R7

I/O

13

3.3V



Y18

IO_L13P_T2_MRCC_13

VIDEO_OUT1_SYNC

I/O

13

3.3V



Y15

IO_L12N_T1_MRCC_13

VIDEO_OUT1_VSYNC

I/O

13

3.3V



Information about the ADV7125KSTZ140 is available on the Analog Devices website.
Note: The TEC0097 evaluation board does not support Display Data Channel, or DDC for display detection.

I2C Bus

The TEC0097 evaluation board implements two I2C ports on the XC7Z015 AP SoC. First port is dedicated to on-board EEPROM at U5 and second port is dedicated to FMC connector at J2. Both port is located on MIO_501 and operating voltage is 1.8V. The EEPROM is 1.8V compatible, while a level shifter is added to the FMC I2C port since it operate with 3.3V on FMC board.
The EEPROM_SDA/SCL pins are wired to the I2C_0 and FMC I2C SDA/SCL pins are wired to the I2C_1 IP controller block within the XC7Z015 AP SoC PS I/O Peripherals set. The EEPEOM device is CAT24C512YI-G and its hardware address is set to 0b1010000.
Table ‎1 15 lists the I2C connections between the XC7Z015 AP SoC PS Bank 501 and the I2C EEPROM component, the FMC I2C detail is given in the FMC section.
{*}Table ‎1* 15: I2C connections between the XC7Z015 and on-board EEPROM

Pin Designator

Pin Name

Net

Type

Bank No.

Bank Voltage

Comment

D10

PS_MIO50_501

EEPROM_SCL

I/O

MIO 501

1.8V



C13

PS_MIO51_501

EEPROM_SDA

I/O

MIO 501

1.8V



For additional information on the Zynq-7000 AP SoC device I2C controller, see Zynq-7000 All Programmable SoC Overview (DS190) and Zynq-7000 All Programmable SoC Technical Reference Manual (UG585).

Status LEDs

The TEC0097 evaluation board supports four general LEDs connected to indicate the board power status and XC7Z015 AP SoC status. Table ‎1 16 lists the LED connections to indicate power and XC7Z015 AP SoC configuration status.
{*}Table ‎1* 16: Status LEDs

LED

Color

Silk Note

Comment

D8

RED

PG

Power Good

D2

RED

POWER

Main 5V power indicator

D3

GREEN

DONE

FPGA configuration done indicator

D13

RED

INIT

FPGA configuration initiate indicator

Note: There are other status LEDs specific to each part of the board, which is described in own section.

GPIO LEDs, Pushbuttons, and DIP Switch

The GPIO including LEDs, Push buttons, and DIP Switch are connected to the XC7Z015 AP SoC PL-side and PS-side. Figure ‎1 16 shows the GPIO connection concept and shows the connection detail.

{*}Figure ‎1* 18: GPIO connection to XC7Z015
For each LED on PL or PS side a driver transistor is added to reduce current drawn from XC7Z015 pins. Figure ‎1 17 shows connection and components for one LED.

{*}Figure ‎1* 19: For each LED a driver transistor is added.
A 2x6 pin header J13 is used as two 4 bit group for user logic extension. First group of 4 bit extension is connected to PS side and second group is connected to PL side. Figure ‎1 18 shows the pin header side signal names, connection to XC7Z015 AP SoC described in the following sections.

{*}Figure ‎1* 20: Extension pin header side signal names

PS-side GPIO

PS GPIO include 2 LEDs, a pushbutton, and 4 bit extension through a pin header (J13). The user push button is active high. Table ‎1 17 shows the GPIO connection detail.
{*}Table ‎1* 17: PS-side GPIO connection detail

Pin Designator

Pin Name

Net

Type

Part No.

Bank Voltage

Comment

B17

PS_MIO14_500

PS_EXT0

I/O

MIO 500

3.3V



C18

PS_MIO12_500

PS_EXT1

I/O

MIO 500

3.3V



E17

PS_MIO15_500

PS_EXT2

I/O

MIO 500

3.3V



B19

PS_MIO11_500

PS_EXT3

I/O

MIO 500

3.3V



G16

PS_MIO10_500

PS_LED1

I/O

MIO 500

3.3V



C19

PS_MIO9_500

PS_LED2

I/O

MIO 500

3.3V



A17

PS_MIO13_500

PS_PB0

I/O

MIO 500

3.3V



PL-side GPIO

It include 4 LEDs, a pushbutton, 4 bit DIP switch, and 4 bit extension through a pin header (J13) connected to PL-side. The user push button is active high and DIP switch is sending logic "1" when set in ON position. Table ‎1 18 shows the GPIO connection detail.
{*}Table ‎1* 18: PL-side GPIO connection detail

Pin Designator

Pin Name

Net

Type

Bank No.

Bank Voltage

Comment

AB17

IO_L17N_T2_13

PL_EXT0

I/O

13

3.3V



AA17

IO_L14N_T2_SRCC_13

PL_EXT1

I/O

13

3.3V



AB18

IO_L16P_T2_13

PL_EXT2

I/O

13

3.3V



AB19

IO_L16N_T2_13

PL_EXT3

I/O

13

3.3V



N8

IO_L5P_T0_34

PL_ID0

I/O

34

VCCADJ



P8

IO_L5N_T0_34

PL_ID1

I/O

34

VCCADJ



M8

IO_L6P_T0_34

PL_ID2

I/O

34

VCCADJ



H8

IO_0_VRN_34

PL_ID3

I/O

34

VCCADJ



R7

IO_L24N_T3_34

PL_LED1

I/O

34

VCCADJ



P7

IO_L24P_T3_34

PL_LED2

I/O

34

VCCADJ



AB14

IO_L9N_T1_DQS_13

PL_LED3

I/O

13

3.3V



AB13

IO_L9P_T1_DQS_13

PL_LED4

I/O

13

3.3V



R4

IO_L23N_T3_34

PL_USER_PB0

I/O

34

VCCADJ





User PMOD GPIO Headers

The TEC0097 evaluation board GPIO includes a 2x6 male headers J8 support Digilent Pmod Peripheral Modules. Figure ‎1 19 shows the circuit implemented for PMOD support, the connector include signals as well as power signals.

{*}Figure ‎1* 21: Digilent Pmod Peripheral Modules support
The connections between the Pmod and the XC7Z015 AP SoC PL-side are listed in Table ‎1 19.
{*}Table ‎1* 19: connections between the Pmod and the XC7Z015 AP SoC

Pin Designator

Pin Name

Net

Type

Bank No.

Bank Voltage

Comment

B8

IO_L7N_T1_AD2N_35

PMOD_1_LVDS_N

I/O

35

VCCADJ



C8

IO_L7P_T1_AD2P_35

PMOD_1_LVDS_P

I/O

35

VCCADJ



A6

IO_L9N_T1_DQS_AD3N_35

PMOD_2_LVDS_N

I/O

35

VCCADJ



A7

IO_L9P_T1_DQS_AD3P_35

PMOD_2_LVDS_P

I/O

35

VCCADJ



A4

IO_L10N_T1_AD11N_35

PMOD_3_LVDS_N

I/O

35

VCCADJ



A5

IO_L10P_T1_AD11P_35

PMOD_3_LVDS_P

I/O

35

VCCADJ



G1

IO_L24N_T3_AD15N_35

PMOD_4_LVDS_N

I/O

35

VCCADJ



H1

IO_L24P_T3_AD15P_35

PMOD_4_LVDS_P

I/O

35

VCCADJ



See the Digilent website for information on Digilent Pmod Peripheral Modules.

Switches

The TEC0097 evaluation board includes a power and a configuration reset (PL PROG_B) and system reset switch:
• Power On/Off slide switch S1
• S3 (FPGA_PROG_B), active-Low pushbutton
• S4 PS System Reset Pushbuttons

Power On/Off Slide Switch

The TEC0097 evaluation board power switch is S1. Sliding the switch actuator from the Off to On position applies 12V power from either J3, an external power barrel connector or PCI Express™ slot. Red LED D2 illuminates when the TEC0097 evaluation board power is on. See TEC0097 Board Power System for details on the onboard power system. The ZPFC evaluation kit provides a 12V external power supply.
Note: Do not to connect external power J3, when TEC0097 is inserted in PCI Express™ slot.

Program_B Pushbutton

Push button S3 grounds the XC7Z015 AP SoC PROG_B pin when pressed. This action clears the programmable logic configuration. The FPGA_PROG_B signal is connected to XC7Z015 AP SoC U6 pin V10.
See 7 Series FPGAs Configuration User Guide, (UG470) for further details on configuring the 7 series FPGAs.

PS Power-On and System Reset Pushbuttons

After applying 12V power D2 LED (POWER) turns on, then after power sequence for on-board power system D8 LED (PG) turns on. This PG (Power Good) is also used to initiate POR (Power On Reset) circuitry of XC7Z015-1CLG485C AP SoC.
Push button S4 grounds the XC7Z015 AP SoC PS_SRST_B pin when pressed. This action reset the processing system of the XC7Z015 AP SoC and initiate the boot process. For more detail on booting refer to Device Configuration and Booting.

FPGA Mezzanine (FMC) Card Interface

The TEC0097 evaluation board supports the VITA 57.1 FPGA Mezzanine Card (FMC) specification by providing full implementations of the low pin count (LPC) version at J2. The connector uses a 10 x 40 form factor, Samtec ASP-134603-01. The LPC connector is partially populated with 160 pins. The connector is keyed so that a mezzanine card, when installed in the FMC connectors on the TEC0097 evaluation board, faces away from and in parallel to the TEC0097 board.
Connector type is Samtec SEAF Series, 1.27 mm (0.050 in) pitch, ASP-134603-01 CC-LPC-10. Mates with SEAM series connector. More information about SEAF series connectors is available at the Samtec website.
More information about the VITA 57.1 FMC specification is available at the VITA FMC Marketing Alliance website.

FMC LPC Connector

The 160-pin LPC connector defined by the FMC specification provides connectivity for up to:
• 68 single-ended or 34 differential user-defined signals
• 1 GTX transceiver
• 1 GTX clock
• 2 differential clocks
• 61 ground and 10 power connections
Table ‎1 20 shows the FMC LPC connections between J2 (ASP-134603-01) and XC7Z015 AP SoC U6.
{*}Table ‎1* 20: FMC LPC connections between J2 and XC7Z015 AP SoC

Pin Designator

Pin Name

Net

Type

Part No.

Bank Voltage

Comment

T1

IO_L13N_T2_MRCC_34

GBTCLK0_M2C_N

I/O

2

VCCADJ



T2

IO_L13P_T2_MRCC_34

GBTCLK0_M2C_P

I/O

2

VCCADJ



L4

IO_L12N_T1_MRCC_34

CLK0_M2C_N

I/O

2

VCCADJ



L5

IO_L12P_T1_MRCC_34

CLK0_M2C_P

I/O

2

VCCADJ



B3

IO_L13N_T2_MRCC_35

CLK1_M2C_N

I/O

3

VCCADJ



B4

IO_L13P_T2_MRCC_35

CLK1_M2C_P

I/O

3

VCCADJ



Y4

MGTXTXN1_112

DP0_C2M_N

Output

7

1.2V



W4

MGTXTXP1_112

DP0_C2M_P

Output

7

1.2V



Y8

MGTXRXN1_112

DP0_M2C_N

Input

7

1.2V



W8

MGTXRXP1_112

DP0_M2C_P

Input

7

1.2V



C4

IO_L12N_T1_MRCC_35

LA00_CC_N

I/O

35

VCCADJ



D5

IO_L12P_T1_MRCC_35

LA00_CC_P

I/O

35

VCCADJ



C5

IO_L11N_T1_SRCC_35

LA01_CC_N

I/O

35

VCCADJ



C6

IO_L11P_T1_SRCC_35

LA01_CC_P

I/O

35

VCCADJ



P5

IO_L20N_T3_34

LA02_N

I/O

34

VCCADJ



P6

IO_L20P_T3_34

LA02_P

I/O

34

VCCADJ



B6

IO_L8N_T1_AD10N_35

LA03_N

I/O

35

VCCADJ



B7

IO_L8P_T1_AD10P_35

LA03_P

I/O

35

VCCADJ



E7

IO_L1N_T0_AD0N_35

LA04_N

I/O

35

VCCADJ



F7

IO_L1P_T0_AD0P_35

LA04_P

I/O

35

VCCADJ



D8

IO_L3N_T0_DQS_AD1N_35

LA05_N

I/O

35

VCCADJ



E8

IO_L3P_T0_DQS_AD1P_35

LA05_P

I/O

35

VCCADJ



B1

IO_L18N_T2_AD13N_35

LA06_N

I/O

35

VCCADJ



B2

IO_L18P_T2_AD13P_35

LA06_P

I/O

35

VCCADJ



G7

IO_L4N_T0_35

LA07_N

I/O

35

VCCADJ



G8

IO_L4P_T0_35

LA07_P

I/O

35

VCCADJ



G2

IO_L22N_T3_AD7N_35

LA08_N

I/O

35

VCCADJ



G3

IO_L22P_T3_AD7P_35

LA08_P

I/O

35

VCCADJ



E3

IO_L21N_T3_DQS_AD14N_35

LA09_N

I/O

35

VCCADJ



E4

IO_L21P_T3_DQS_AD14P_35

LA09_P

I/O

35

VCCADJ



D2

IO_L17N_T2_AD5N_35

LA10_N

I/O

35

VCCADJ



E2

IO_L17P_T2_AD5P_35

LA10_P

I/O

35

VCCADJ



K5

IO_L7N_T1_34

LA11_N

I/O

34

VCCADJ



J5

IO_L7P_T1_34

LA11_P

I/O

34

VCCADJ



F4

IO_L20N_T3_AD6N_35

LA12_N

I/O

35

VCCADJ



G4

IO_L20P_T3_AD6P_35

LA12_P

I/O

35

VCCADJ



C1

IO_L16N_T2_35

LA13_N

I/O

35

VCCADJ



D1

IO_L16P_T2_35

LA13_P

I/O

35

VCCADJ



F1

IO_L23N_T3_35

LA14_N

I/O

35

VCCADJ



F2

IO_L23P_T3_35

LA14_P

I/O

35

VCCADJ



K2

IO_L9N_T1_DQS_34

LA15_N

I/O

34

VCCADJ



J3

IO_L9P_T1_DQS_34

LA15_P

I/O

34

VCCADJ



D6

IO_L2N_T0_AD8N_35

LA16_N

I/O

35

VCCADJ



D7

IO_L2P_T0_AD8P_35

LA16_P

I/O

35

VCCADJ



C3

IO_L14N_T2_AD4N_SRCC_35

LA17_CC_N

I/O

35

VCCADJ



D3

IO_L14P_T2_AD4P_SRCC_35

LA17_CC_P

I/O

35

VCCADJ



A1

IO_L15N_T2_DQS_AD12N_35

LA18_CC_N

I/O

35

VCCADJ



A2

IO_L15P_T2_DQS_AD12P_35

LA18_CC_P

I/O

35

VCCADJ



N5

IO_L19N_T3_VREF_34

LA19_N

I/O

34

VCCADJ



N6

IO_L19P_T3_34

LA19_P

I/O

34

VCCADJ



E5

IO_L5N_T0_AD9N_35

LA20_N

I/O

35

VCCADJ



F5

IO_L5P_T0_AD9P_35

LA20_P

I/O

35

VCCADJ



K8

IO_L1N_T0_34

LA21_N

I/O

34

VCCADJ



J8

IO_L1P_T0_34

LA21_P

I/O

34

VCCADJ



J6

IO_L2N_T0_34

LA22_N

I/O

34

VCCADJ



J7

IO_L2P_T0_34

LA22_P

I/O

34

VCCADJ



H3

IO_L19N_T3_VREF_35

LA23_N

I/O

35

VCCADJ



H4

IO_L19P_T3_35

LA23_P

I/O

35

VCCADJ



M3

IO_L22N_T3_34

LA24_N

I/O

34

VCCADJ



M4

IO_L22P_T3_34

LA24_P

I/O

34

VCCADJ



K3

IO_L11N_T1_SRCC_34

LA25_N

I/O

34

VCCADJ



K4

IO_L11P_T1_SRCC_34

LA25_P

I/O

34

VCCADJ



M6

IO_L4N_T0_34

LA26_N

I/O

34

VCCADJ



L6

IO_L4P_T0_34

LA26_P

I/O

34

VCCADJ



J1

IO_L8N_T1_34

LA27_N

I/O

34

VCCADJ



J2

IO_L8P_T1_34

LA27_P

I/O

34

VCCADJ



N3

IO_L21N_T3_DQS_34

LA28_N

I/O

34

VCCADJ



N4

IO_L21P_T3_DQS_34

LA28_P

I/O

34

VCCADJ



L1

IO_L10N_T1_34

LA29_N

I/O

34

VCCADJ



L2

IO_L10P_T1_34

LA29_P

I/O

34

VCCADJ



R2

IO_L17N_T2_34

LA30_N

I/O

34

VCCADJ



R3

IO_L17P_T2_34

LA30_P

I/O

34

VCCADJ



M1

IO_L15N_T2_DQS_34

LA31_N

I/O

34

VCCADJ



M2

IO_L15P_T2_DQS_34

LA31_P

I/O

34

VCCADJ



U1

IO_L14N_T2_SRCC_34

LA32_N

I/O

34

VCCADJ



U2

IO_L14P_T2_SRCC_34

LA32_P

I/O

34

VCCADJ



P1

IO_L16N_T2_34

LA33_N

I/O

34

VCCADJ



N1

IO_L16P_T2_34

LA33_P

I/O

34

VCCADJ



G6

IO_L6P_T0_35

PRSNT_M2C_L

I/O

35

VCCADJ



M7

IO_L6N_T0_VREF_34

VREF_A_M2C

I/O

34

VCCADJ



F6

IO_L6N_T0_VREF_35

VREF_A_M2C

I/O

35

VCCADJ



D12

PS_MIO48_501

MIO_FMC_SCL

I/O

MIO 501

1.8V



C9

PS_MIO49_501

MIO_FMC_SDA

I/O

MIO 501

1.8V





FMC I2C Port

The I2C signals of FMC LPC is connected to XC7Z015 AP SoC I2C 1 IP controller, Table ‎1 20 shows the connection detail. The port is located on MIO_501 and operating voltage is 1.8V, a level shifter is added to the FMC I2C port since it operate with 3.3V.
Note: LPC FMC (J2) GA0 = GA1 = 0 = GND.

FMC Presence Detect

The PRSNT_M2C_L is connected to pin G6 in bank 35 of XC7Z015. As active low signal, it can be used as FMC card presence detector.

FMC VADJ Voltage Control

Along with on-board power system, the VCCADJ of FMC connector is provided by a separate DC-DC converter. The VCCADJ is also used to supply bank 13 and 34 of XC7Z015 AP SoC. For more information for on-board power system, refer to TEC0097 Board Power System.
The TEC0097 used EN5335QI at U24 as VCCADJ DC-DC converter in which enable and voltage value is selectable using a DIP switch S2. Table ‎1 21 shows the settings for enable/disable and voltage settings.
{*}Table ‎1* 21: THE VCCADJ setting

SW2.3

SW2.2

SW2.1

SW2.4

Voltage

Comment

0

0

0

0

3.3V

enabled

0

0

1

0

2.5V

enabled

0

1

0

0

1.8V

enabled

0

1

1

0

1.5V

enabled

1

0

0

0

1.25V

enabled

x

x

x

1

-

disabled

Note: The VCCADJ is used to supply bank 13 and 34 of XC7Z015, so disabling it will turn off banks 13 and 34, and associated IOs as well.

TEC0097 Board Power System

The TEC0097 board hosts a power system based on the Texas Instruments the LMZ23605 and Analog Devices ADP5052 family of voltage regulators.
The LMZ23605 SIMPLE SWITCHER® power module is a step-down DC-DC solution capable of driving up to 5A load. The LMZ23605 module can accept an input voltage rail between 6V and 36V and deliver an adjustable and highly accurate output voltage as low as 0.6V.
The LMZ23605 SIMPLE SWITCHER® power module is a step-down DC-DC solution capable of driving up to 5A load. These modules only requires two external resistors plus external capacitors to provide a complete power solution. These modules offer the following protection features: thermal shutdown, programmable input under-voltage lockout, output over-voltage protection, short-circuits protection, output current limit, and each allows startup into a pre-biased output.
The ADP5052 combines four high performance buck regulators and one 200 mA low dropout (LDO) regulator in a 48-lead LFCSP package that meets demanding performance and board space requirements. The device enables direct connection to high input voltages up to 15 V with no preregulators.
Channel 1 and Channel 2 integrate high-side power MOSFETs and low-side MOSFET drivers. External NFETs can be used in low-side power devices to achieve an efficiency optimized solution and deliver a programmable output current of 1.2 A, 2.5 A, or 4 A. Combining Channel 1 and Channel 2 in a parallel configuration can provide a single output with up to 8 A of current.
Channel 3 and Channel 4 integrate both high-side and low-side MOSFETs to deliver output current of 1.2 A.
The TEC0097 evaluation board can be supplied from two source: PCI Express slot or external 12V through power connector. Care should be taken not to connect external power when TEC0097 is inserted in PCIe slot. The power distribution diagram and deployed components list is shown in Figure ‎1 20.

{*}Figure ‎1* 22: The TEC0097 evaluation board power distribution diagram
A RED LED, D8, illuminate when all power with appropriate sequence turn on, to indicate PG power good signal, it is used to reset the CPU as well.

{*}Figure ‎1* 23: On-board power sequence
For more information on power rails refer to I/O Voltage Rails, and for more information on VCCADJ refer to FMC VADJ Voltage Control.

XADC Analog-to-Digital Converter

The XC7Z015 AP SoC provides an Analog Front End XADC block. The XADC block includes a dual 12-bit, 1 MSPS Analog-to-Digital Convertor (ADC) and on-chip sensors. See 7 Series FPGAs and Zynq-7000 All Programmable SoC XADC Dual 12-Bit 1 MSPS Analog-to-Digital Converter User Guide (UG480) for details on the capabilities of the analog front end.
The TEC0097 evaluation board supports both the internal XC7Z015 AP SoC sensor measurements and the external measurement capabilities of the XADC. Internal measurements of the die temperature, VCCINT, VCCAUX, and VCCBRAM are available.
For external measurements an PMOD header (J8) is provided. This header can be used to provide analog inputs to the XC7Z015 AP SoC's dedicated VP/VN of auxiliary analog input channels. Simultaneous sampling of Channel 0 and Channel 8 is supported.

Default Switch and Jumper Settings

The default switch and jumper settings for the TEC0097 evaluation board are provided in this section. It is recommended to check the switch and jumper setting before using the board.

Switches

There are one slide switch and three DIP switch on the TEC0097 evaluation board. Default switch settings are listed in Table ‎2 1, for more detail refer to associated board section.
{*}Table ‎2* 1: Switch setting on the TEC0097 evaluation board

Name

Label on Board

Purpose

Board Section (Refer to)

Default Setting

S1

ON/OFF

Power ON/OFF

TEC0097

OFF

S7

MODE

Configuration mode select

Device Configuration and Booting

00 (JTAG)

S2

VADJ

Adjust VADJ voltage for FMC

FMC VADJ Voltage Control

0000 (3.3V)

S5

PL

PL-side user DIP switch

PL-side GPIO

0000

Jumpers

The TEC0097 evaluation board, include one jumper J7 which is FMC JTAG loopback jumper. Refer to JTAG Programming Processor and Programmable Logic for more information about JTAG loop. If user want to use TEC0097 without FMC card, jumper should be placed at J7.

Software Getting Started

Set-up Considerations

Appendix A: Referenced Documents
The most up to date information related to the TEC0097 board, its documentation, and schematics, are available on the following websites.
These Xilinx documents provide supplemental material useful with this guide:

  1. Zynq-7000 All Programmable SoC Overview (DS190)

  2. LogiCORE IP Tri-Mode Ethernet MAC Product Guide for Vivado Design Suite (PG051)

  3. 7 Series FPGAs Memory Resources User Guide (UG473)

  4. 7 Series FPGAs Configuration User Guide (UG470)

  5. 7 Series FPGAs GTX/GTH Transceivers User Guide (UG476)

  6. 7 Series FPGAs Integrated Block for PCI Express Product Guide (PG054)

  7. 7 Series FPGAs and Zynq-7000 All Programmable SoC XADC Dual 12-Bit 1 MSPS Analog-to-Digital Converter User Guide (UG480)

  8. Zynq-7000 All Programmable SoC Technical Reference Manual (UG585)

  9. 7 Series FPGAs Memory Interface Solutions User Guide (UG586)

  10. Zynq-7000 All Programmable SoC Packaging and Pinout Product Specification (UG865)

  11. Vivado Design Suite User Guide: Using Constraints (UG903)

  12. Zynq-7000 All Programmable SoC PCB Design and Pin Planning Guide (UG933)


Documents associated with other devices used by the TEC0097 evaluation board are available at these vendor websites:

  1. Standard Microsystems Corporation: www.smsc.com/ (USB3320)

  2. SD Association: www.sdcard.org.

  3. PCI Express® standard: www.pcisig.com/specifications

  4. Analog Devices: www.analog.com/ (ADP5052ACPZ, ADV7511KSTZ, ADM3078E)

  5. Texas Instruments: www.ti.com, (LMZ23605TZ, TPS74801, TPS51200DR, TCA9406DCUR, TXS02612, DP83867CRRGZT)

  6. Altera, https://www.altera.com, (EN5335QI)

  7. Samtec: www.samtec.com. (ASP-134603-01, SEAF series connectors)

  8. Micron Technology: www.micron.com (MT41K256M16HA-125AIT, N25Q256A11ESF40G)

  9. Digilent: www.digilentinc.com (Pmod Peripheral Modules)

  10. VITA FMC Marketing Alliance: www.vita.com (FPGA Mezzanine Card (FMC) VITA 57.1 specification)

  11. Future Technology Devices International: www.ftdichip.com, (FT2232H-56Q)